GL852GC 電子元器件 GENESYS/創(chuàng)惟科技 封裝LQFP-48USB 2.0 MTT集線器控制器

　　DESCRIPTION

　　GL852G is Genesys Logic’s premium 4-port hub solution which fully complies with Universal Serial Bus Specification Revision 2.0. GL852G implements multiple TT* (Note1) architecture that provide dedicated TT* to each downstream (DS) ports, which guarantee Full-Speed(FS) data passing bandwidth when multiple FS device perform heavy loading operations. The controller inherits Genesys Logic’s cutting edge technology on cost and power efficient serial interface design. GL852G has proven compatibility, lower power consumption figure and better cost structure above all USB2.0 hub solutions worldwide.

　　GL852G implements multiple hub configuration features onto internal mask ROM, which traditionally requires one external EEPROM. The microprocessor detects general purpose I/O (GPIO) status during the initial stage to configure hub settings such as (1) number of DSport, (2) declare of compound device (3) gang/individual mode selection…etc. External EEPROM can be removed if no vendor specified PID/VID or product string is required for the application.

　　GL852G supports three package types, summarized as below table. LQFP48 package provides full hub features such as (1) two-color (green/amber) status LEDs for each DS ports, (2) Individual/Gang mode power management scheme that indicates DS port over-current events. (3) Number of DS ports setting configured by GPIO setting (4) non-removable declaration configured by GPIO setting (5) Support both 93C46 and 24C02 EEPROM (6) power switch polarity selections…etc. QFN28/SSOP28 package support only partial hub features but provide smaller footprint that targets space limited PCB layout environments such as embedded system or UMPC/MID applications.

　　FEATURES

　　Compliant to USB specification Revision 2.0

　　4 downstream ports

　　Upstream port supports both high-speed (HS) and full-speed (FS) traffic

　　Downstream ports support HS, FS, and low-speed (LS) traffic

　　1 control pipe (endpoint 0, 64-byte data payload) and 1 interrupt pipe (endpoint 1, 1-byte data payload)

　　Backward compatible to USB specification Revision 1.1

　　On-chip 8-bit micro-processor

　　RISC-like architecture

　　USB optimized instruction set

　　Dual cycle instruction execution

　　Performance: 6 MIPS @ 12MHz

　　With 64-byte RAM and 9K internal ROM

　　Support customized PID, VID by reading external EEPROM

　　Support downstream port configuration by reading external EEPROM

　　Multiple Transaction translator (MTT)

　　MTT provides respective TT control logics for each downstream port.

　　Each downstream port supports two-color status indicator, with automatic and manual modes compliant to USB specification Revision 2.0

　　Built-in upstream port 1.5KΩ pull-up and downstream port 15KΩ pull-down resistors

　　Support both individual and gang modes of power management and over-current detection for downstream ports

　　Conform to bus power requirements of USB 2.0 specification

　　Automatic switching between self-powered and bus-powered modes

　　Integrate USB 2.0 transceiver

　　Embedded PLL support external 12 MHz crystal / Oscillator clock input

　　Optional 27/48 MHz Oscillator clock input (Only available in LQFP48 package)

　　Support compound-device (non-removable in downstream ports) by I/O pin configuration (Only available in LQFP48 package)

　　Number of Downstream port can be configured by GPIO without external EEPROM (Only available in LQFP48 package)

　　Built-in 5V to 3.3V regulator

　　Improve output drivers with slew-rate control for EMI reduction

　　Internal power-fail detection for ESD recovery

　　Available package types: 48 pin LQFP, 28 pin QFN and 28 pin SSOP

　　Applications:

　　Stand-alone USB hub / USB docking

　　UMPC/MID, motherboard on-board applications

　　Consumer electronics built-in hub application

　　Monitor built-in hub

　　Embedded systems

　　Compound device to support USB hub function such as keyboard hub applications